Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that has response (read/write) times comparable to volatile memory. In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. As illustrated in FIGS. 1A and 1B, a magnetic tunnel junction (MTJ) storage element 100 can be formed from two magnetic layers 110 and 130, each of which can hold a magnetic moment, separated by an insulating (tunnel barrier) layer 120. One of the two layers (e.g., fixed layer 110), is set to a particular polarity. The other layer's (e.g., free layer 130) polarity 132 is free to change to match that of an external magnetic field that can be applied. A change in the polarity 132 of the free layer 130 will change the resistance of the MTJ storage element 100. For example, when the magnetization polarities are aligned, FIG. 1A, a low resistance state exists (parallel “P” magnetization low resistance state “0”). When the magnetization polarities are not aligned, FIG. 1B, then a high resistance state exists (anti-parallel “AP” magnetization high resistance state “1”). The illustration of MTJ 100 has been simplified and those skilled in the art will appreciate that each layer illustrated may comprise one or more layers of materials, as is known in the art. For example, one or more additional layers made of anti-ferromagnetic materials may be added on top of free layer 130 in order to improve the speed and efficiency of switching of the free layer.
Referring to FIG. 2, a memory cell 200 of a conventional MRAM is illustrated for a read operation. The cell 200 includes a transistor 210, bit line 220, digit or source line 230 and word line 240. The cell 200 can be read by measuring the electrical resistance of the MTJ 100. For example, a particular MTJ 100 can be selected by activating an associated transistor 210 (transistor on), which can switch current from a bit line 220 through the MTJ 100. Due to the tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the magnetization polarities in the two magnetic layers (e.g., 110, 130), as discussed above. The resistance inside any particular MTJ 100 can be determined from the current, resulting from the magnetization polarity of the free layer. Conventionally, if the fixed layer 110 and free layer 130 have the same magnetization polarity, the resistance is low and a “0” is read. If the fixed layer 110 and free layer 130 have opposite magnetization polarity, the resistance is higher and a “1” is read.
Unlike conventional MRAM, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is known in the art, where an STT-MRAM bit cell uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM). During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the magnetization polarity of the free layer. The read operation is similar to conventional MRAM in that a current is used to detect the resistance/logic state of the MTJ storage element, as discussed in the foregoing. As illustrated in FIG. 3A, a STT-MRAM bit cell 300 includes MTJ 305, transistor 310, bit line 320 and word line 330. Transistor 310 is turned on for both read operations and write operations, in order to allow current to flow through MTJ 305, so that the logic state can be read or written.
Referring to FIG. 3B, a more detailed diagram of a STT-MRAM cell 301 is illustrated, for further discussion of the read/write operations. In addition to the previously discussed elements such as MTJ 305, transistor 310, bit line 320 and word line 330, source line 340, sense amplifier 350, read/write circuitry 360 and bit line reference 370 are illustrated. As discussed above, during a read operation, a read current is generated, which flows between the bit line 320 and source line 340 through MTJ 305. When the current is permitted to flow via transistor 310, the resistance (logic state) of the MTJ 305 can be sensed based on the voltage differential between the bit line 320 and source line 340, which is compared to a reference 370 and then amplified by sense amplifier 350. Those skilled in the art will appreciate the operation and construction of the memory cell 301 is known in the art.
With reference now to FIG. 4, a memory array comprising STT-MRAM cells, such as, cell 300 of FIG. 3A, is illustrated. As shown herein, each bit cell has 3 terminals, viz., a word-line select terminal (WL[*]), a bit-line terminal (BL[*]), and a source-line terminal (SL[*]). This cell structure with a single access transistor such as transistor 310 of FIG. 3B is referred to as a 1T1J (one-transistor-one-MTJ) implementation, which is known to consume approximately one-half to one-fourth of the area consumed by conventional SRAM cells. As shown, the transistors are used to switch on or off the connection between the MTJ and SL[i], where the transistors are controlled by the word-line select terminals respectively.
In more detail, during write operations, the MTJs of the STT-MRAM bit cells are configured as programmable resistors of value of ˜2.5-5K ohms. For writing a particular bit cell, the corresponding selected word line is asserted and all unselected word lines are de-asserted. Appropriate voltages for the value to be written are set on BL[0, 1, 2 . . . ] and SL[0, 1, 2 . . . ]. An overdrive voltage may be applied on the transistor gate to avoid the gate-drain voltage of the transistor (Vgd) to drop to zero, as write operations are bi-polar (i.e., current flows in one direction for writing logic 0, and flows in the opposite direction for writing logic 1). Further, the write operations on STT-MRAM bit cells typically require a relatively large current (˜150 uA) due to the STT spin polarized current described previously.
In the case of read operations on a bit cell [i] for example, the corresponding selected word line is asserted and all unselected word lines are de-asserted. Both corresponding BL[i] and SL[i] are connected to a sensing circuit [i] (e.g., sense amplifier 350 of FIG. 3B), and the current flow is compared with the reference (e.g., reference 370 of FIG. 3B). If the current is greater than the reference, then logic 0 is sensed, otherwise logic 1 is sensed. For read operations, there is no need for gate overdrive voltage, as read operations are uni-polar.
While STT-MRAM technology offers significant improvements over conventional SRAM technology for non-volatile memory cells, for example, in terms of size, speed, cost, area, etc., advances in the area of magnetic cells have been made, which allow for further improvements in these regards. For example, one such advancement is observed in the case of magnetic cells which utilize a so-called spin Hall effect (SHE).
With reference to FIG. 5A, SHE is demonstrated in conductor 500. Electrons 509 passing through conductor 500 in the direction indicated, get polarized on the surfaces 502, 504, 506, and 508 along the directions indicated by arrows 501, 503, 505, and 507 respectively due to spin-orbit coupling. A spin Hall ratio is defined as
      θ    SH    =                    Js        ⁢                  /                ⁢                  (                      ℏ            ⁢                                                  ⁢            h            ⁢                          /                        ⁢            2                    )                            Jc        ⁢                  /                ⁢        e              .  
While SHE can be used to induce magnetic polarity along the directions 501, 503, 505, and 507, the effect can be improved by using special material (such as beta-tungsten) with appropriate thickness (such as thickness of just a few nanometers) for conductor 500, for example, as described in Pai et al. published as “Spin transfer torque devices utilizing the giant spin Hall effect of tungsten,” Applied Physics Letters, §101, 122404, 2012 (hereinafter, the Pai reference). In more detail FIG. 5B illustrates conductor 500 with length (L), thickness (t) and width (W), wherein, with reference to Pai, an improvement θSH is shown in orders of magnitude, up to ˜0.33 times. This leads to a so-called giant spin Hall effect (GHSE).
The spin current generation efficiency is provided by the following equation:
                    I        S                    I        C              =                            Js          A                          Jc          a                    =                                    θ            SH                    ⁢                      A            a                          =                              θ            SH                    ⁢                      L            t                                ,where “IS” is the spin current a “IC” is the charge current. The spin current generation efficiency IS/IC can be further boosted by making appropriate changes to dimensions of conductor 500. For example, for a value of θSH=0.30, L=50-100 nm, and t=2 nm, it is seen that the ratio IS/IC can be as high as 7.5-15. This spin current generation efficiency in the order of ˜7.5-15, can be typical, considering that the ratio of L/t is ˜25-50, is typical for cases where the thickness “t” is only a few nanometers whereas the length “L” is in the order of tens of nanometers. In comparison, the spin current generation efficiency from STT polarization is merely ˜0.6.
Further, the θSH has improved over three orders of magnitude (˜1000×) to ˜0.3 based on the past few years' advances in SHE material research as shown in FIG. 5C (derived from Spintronics Research at Cornell University by Liu et al.), particularly for conductor materials such as beta-tungsten, beta-tantalum, and platinum, etc. These improvements relate to reasons why GSHE is considered to be “giant” in comparison to previously demonstrated SHE. The GSHE provides an efficient method to convert electric current based on electrons 509 into spin current, which can be used for providing switching current to MTJ cells.
Moreover, in comparison to STT-MRAMs, with the same resistance of the MTJ, the programming power using the GHSE effect can be approximately 50-200 times lower, which means that it is easier to write MTJs based on GHSE, which in turn, translates into smaller memory cells and high memory density. Moreover, a cap for the write current (Iwrite) observed for STT-MRAM (in order to avoid breakdown of the tunnel or barrier layer) is eliminated using GHSE. As shown, a magnetic element 510 placed on top of conductor 500 can get polarized in the direction indicated by arrow 501. As previously described, the ratio IS/IC can be varied by adjusting area A (=L*w) or area a (=t*w), or in other words, by adjusting the ratio, L/t. If magnetic material 510 is placed in the orientation shown, where width W is wider than thickness t, the direction 501 influences the polarization of magnetic material 510. More specifically, when magnetic material 510, configured as a free layer, is placed on top of conductor 500, configured as a spin-orbital coupling layer, the spin orientation 501 from spin Hall effect can influence the magnetization of the free layer magnetic material 510.
With reference now to FIG. 6A, a side view of a conventional memory element 600 that is switched (programmed, or written) by SHE (or more specifically GSHE) is illustrated. A SHE/GSHE strip comprising conductor 500 (referred to simply as a GSHE strip 500 in this case), which may be formed from strong spin-orbit coupling material, such as β-W, β-Ta, or Pt is formed between terminals A and B. Terminals A and B may be formed from metals such as copper. An MTJ 601 is placed above the GSHE strip 500, with a free layer of MTJ 601 adjacent to and in contact with GSHE 500. Write current Iw is passed through the GSHE strip in the direction indicated between A and B. Based on the induced spin polarization, the free layer of MTJ 601 can be switched. This provides a much more efficient way of programming MTJ 601 than in the STT-MRAM cell structure 301 illustrated in FIG. 3B. Additionally, in memory element 600, optional layers Ru, and CoFe, and an anti-ferromagnetic layer (AFM), and/or a synthetic antiferromagnetic layer (SAF) along with a top electrode are also depicted as formed on MTJ 601. MTJ 601 is read based on sensing the read current Iread, as will be further explained in following sections.
With reference to FIG. 6B, a top view of MTJ 601 switched by a conventional SHE/GSHE arrangement of FIG. 6A is shown. The direction 602 is perpendicular to the write current from/to terminal A to/from terminal B, and is referred to as the easy axis of MTJ 601. The free layer of MTJ 601 resides at a minimal magneto-static energy region along easy axis 602. In more detail, easy axis orientation is a property of the free layer based on the shape of the free layer. The free layer will always be magnetized along the easy axis when external magnetization force is removed. In conventional SHE switched MTJ, the SHE write current is orthogonal to the easy axis orientation such that the SHE induced spin orientation is in line with easy axis orientation. Thus, easy axis 602 is considered to be oriented along the x direction in FIG. 6B, and is transverse to the direction of write current Iw. On the other hand, hard axis 604 of MTJ 601, which is perpendicular to easy axis 602, is formed along the y direction. The free layer of MTJ 601 interfaces GSHE strip 500 and easy axis 602 is in line with or parallel to the corresponding GSHE induced spin orientation. In other words, the orientation of easy axis 602 of the free layer of MTJ 601 is parallel to the magnetization axis created by electrons traversing GSHE strip 500 between the two terminals A and B. As explained previously, the MTJ is in a low resistance state (P state) if the magnetization of the free layer is aligned (parallel) to the magnetization of the fixed layer; and the MTJ is in a high resistance state (AP state) if the magnetization of the free layer is anti-aligned (anti-parallel) to magnetization of the fixed layer.
With reference to FIG. 6C, an equivalent circuit of conventional SHE/GSHE switched MTJ element 600 is depicted, along with the symbol for the device. Under operational conditions, when the current between terminals A and B is no less than a threshold (˜20 uA), the MTJ switches to state ‘0’ (low MTJ resistance) if current flows from A to B; and to state ‘1’ (high MTJ resistance) if the current flows in the opposite direction, from B to A. When the current between A and B is less than the threshold (˜20 uA), the MTJ retains its previous state (either ‘0’ or ‘1’).
While the above-described conventional SHE/GSHE switched MTJ element 600 exhibits vast improvements over known STT-switched MTJs in STT-MRAM structures, known approaches to utilizing the conventional SHE/GSHE switched MTJ elements suffer various limitations, which will be discussed in detail below. According to the implementations and parameters, the conventional SHE/GSHE switched MTJ elements may be characterized as SHE-switched or GSHE-switched MTJs. In the discussion of these conventional structures, the conventional SHE/GSHE switched MTJ elements (e.g., element 600) have been assumed to be memory elements for SHE-MRAMs, for the sake of generality.
Conventional Implementation 1—1T1J SHE-MRAM
In FIG. 7, a first conventional implementation related to a memory array comprising SHE-MRAM memory cells comprising 1T1J structures (i.e., one access transistor per every memory element comprising an MTJ) is depicted. Each bit cell has 4 terminals: a Word-line Select Terminal, a Write Terminal, a Write Negated Terminal, and a Read Terminal. The conventional implementation for each bit cell [i] involves connecting the Word-line Select Terminal to WL[i], the Write Terminal to WBL[i], the Write Negated Terminal to WBLn[i], and the Read Terminal to RBL[i]. In each memory cell, the connection between the Write Terminal and WBL[i] is switched on/off via the corresponding access transistor controlled by the Word-line Select Terminal.
During a write operation on a particular bit cell (701) the corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are accordingly set for WBL[0, 1, 2 . . . ] and WBLn[0, 1, 2 . . . ], and RBL[0, 1, 2 . . . ] are floated. For the sake of explanation in the entirety of this discussion (unless indicated otherwise), zero resistance is assumed for the current paths where the access transistors are switched on, and an infinite resistance is assumed for the current paths where the access transistors are switched off. Further, for different kinds of paths which may arise in this disclosure, numerical references have been added, which will be explained below in each pertinent section. Accordingly, in FIG. 7, an intended functional current path has write resistance Rwr for the write to bit cell 701, where the intended functional current path is shown with the reference numeral “(1)”. During a write operation on bit cell 701, unintended current paths result for cells 701 and 702, which are indicated with the reference numeral “(2),” each with resistance twice the read resistance Rrd along with Rwr (i.e., 2Rrd+Rwr). In this case, it is noted that even though these unintended paths do not cause write functionality to fail for the write operation, since Rrd is much bigger than Rwr (>10x), they nevertheless collectively consume significant additional power.
In the case of a read operation (on bit cell 704), corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are set on WBL[0, 1, 2 . . . ], and on RBL[0, 1, 2 . . . ] to have current flow from/to WBL[i] to/from RBL[i]; and WBLn[0, 1, 2 . . . ] are floated. The intended functional current path for the read operation is shown with reference numeral “(4),” for cell 704 with resistance Rrd. The unintended paths during the read operation are shown with reference numeral “(3),” for cells 703/704, each with resistance Rrd+Rwr. However, it is noted that in this case, these unintended paths “(3)” during read operations do break read functionality, as the resistance change on the unintended paths can disguise, or be confused with, the resistance of the intended path.
Conventional Implementation 2—1T1J SHE-MRAM
In FIG. 8, a second conventional implementation related to a memory array comprising SHE-MRAM memory cells comprising 1T1J structures, is depicted. Once again, each bit cell has 4 terminals: a Word-line Select Terminal, a Write Terminal, a Write Negated Terminal, and a Read Terminal. The conventional implementation for each bit cell [i] involves connecting the Word-line Select Terminal to WL[i], the Write Terminal to WBL[i], the Write Negated Terminal to WBLn[i], and the Read Terminal to RBL[i]. In this implementation, the connection between the Read Terminal and RBL[i] is switched on/off via a transistor controlled by the Word-line Select Terminal.
During a write operation on a particular bit cell (801) the corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are accordingly set for WBL[0, 1, 2 . . . ] and WBLn[0, 1, 2 . . . ], and RBL[0, 1, 2 . . . ] are floated. Following like reference numerals as FIG. 7, the intended functional current path is indicated as “(1),” for bit cell 801 with resistance Rwr. The unintended paths are shown as “(2),” each with resistance Rwr, for bit cells 801, 802, and 803. However, in this case, it must be noted that the unintended paths do break write functionality, as they induce unintended writes on bit cells 802 and 803.
In the case of a read operation (on bit cell 804), corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are set on WBL[0, 1, 2 . . . ] and RBL[0, 1, 2 . . . ] (while WBLn[0, 1, 2 . . . ], are floated), in order to have current flow from/to WBL[i]/WBLn[i] to/from RBL[i]. For read operations in this implementation, intended functional path is shown as “(4),” with resistance Rrd. There are no unintended paths, and therefore no breaks in read functionality.
Conventional Implementation 3—1T1J SHE-MRAM
In FIG. 9, a third conventional implementation related to a memory array comprising SHE-MRAM memory cells comprising 1T1J structures, is depicted. Once again, each bit cell has 4 terminals: a Word-line Select Terminal, a Write Terminal, a Write Negated Terminal, and a Read Terminal. The conventional implementation for each bit cell [i] involves connecting the Word-line Select Terminal to WL[i], the Write Terminal to WBL[i], the Write Negated Terminal to WBLn[i], and the Read Terminal to RBL[i]. In this case, the connection between the Write Negated Terminal and WBLn[i] is switched on/off via a transistor controlled by the Word-line Select Terminal.
During a write operation on a particular bit cell (901) the corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are accordingly set for WBL[0, 1, 2 . . . ] and WBLn[0, 1, 2 . . . ], and RBL[0, 1, 2 . . . ] are floated. Following similar naming conventions as above, the intended functional current path is shown as “(1),” for bit cell 901 with resistance Rwr The unintended paths are shown as “(2),” for cells 901 and 902, each with resistance 2Rrd+Rwr. The unintended paths during the write operation do not break write functionality, as Rrd is much bigger than Rwr (>10x), although these unintended paths collectively consume significant additional power.
In the case of a read operation (on bit cell 904), corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are set on WBLn[0, 1, 2 . . . ], and on RBL[0, 1, 2 . . . ] to have current flow from/to WBLn[i] to/from RBL[i]. For read operations in this implementation, intended functional path are shown as “(4),” with resistance Rrd. The unintended paths are shown as “(3),” for bit cells 903 and 904, each with resistance Rrd+Rwr. These unintended paths do break read functionality, as the resistance change on unintended paths can disguise that of the intended path.
From the above three conventional implementations, it is seen that the 1T1J structures are fraught with drawbacks which render such implementations unsatisfactory for easy and correct read/write operations on the SHE-MRAM structures. Accordingly, conventional implementations pertaining to 2T1J structures with two access transistors per MTJ for each bit cell are also considered below.
Conventional Implementation 4—2T1J SHE-MRAM
In FIG. 10, a fourth conventional implementation related to a memory array comprising SHE-MRAM memory cells comprising 2T1J structures, is depicted. Once again, each bit cell has 4 terminals: a Word-line Select Terminal, a Write Terminal, a Write Negated Terminal, and a Read Terminal. The conventional implementation for each bit cell [i] involves connecting the Word-line Select Terminal to WL[i], the Write Terminal to WBL[i], the Write Negated Terminal to WBLn[i], and the Read Terminal to RBL[i]. In this case, the connection between the Write Terminal and WBL[i] is switched on/off via a first transistor controlled by the Word-line Select Terminal, and the connection between the Write Negated Terminal and WBLn[i] is switched on/off via a second transistor controlled by the Word-line Select Terminal.
During a write operation on a particular bit cell (1001) the corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are accordingly set for WBL[0, 1, 2 . . . ] and WBLn[0, 1, 2 . . . ], and RBL[0, 1, 2 . . . ] are floated. The intended functional current path is shown as “(1),” with resistance Rwr. There are no unintended paths, and therefore, there are no paths which break write functionality.
Another consideration which arises in this case is related to the transistor gate overdrive requirement due to bi-polar writing. As current flows from/to the Write Terminal to/from the Write Negated Terminal for writing logic 1/0 respectively, with WL[i] set to Vdd, and WBL[i] to Vdd/Vss, and WBLn[i] to Vss/Vdd, one of the two transistors display elevated Vgs, and Vgd=0, thus the drive strength of that transistor is significantly reduced. Accordingly, a typical solution to this reduced drive strength is to overdrive gate line WL[i], which results in a complicated design; or in increased transistor size, which reduces memory density.
In the case of a read operation (on bit cell 1002), corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are set on WBLn[0, 1, 2 . . . ], and on RBL[0, 1, 2 . . . ] to have current flow from/to WBLn[i] to/from RBL[i]. WBLn[0, 1, 2 . . . ] are set to have the same voltages as corresponding WBL[0, 1, 2 . . . ]. For read operations in this implementation, the intended functional path is shown as “(4),” with resistance Rrd. There are no unintended paths, and therefore, no related break in read functionality. Further, there does not arise a need for a transistor gate overdrive, as read operations are uni-polar.
Conventional Implementation 5—2T1J SHE-MRAM
In FIG. 11, a fifth conventional implementation related to a memory array comprising SHE-MRAM memory cells comprising 2T1J structures, is depicted. Once again, each bit cell has 4 terminals: a Word-line Select Terminal, a Write Terminal, a Write Negated Terminal, and a Read Terminal. The conventional implementation for each bit cell [i] involves connecting the Word-line Select Terminal to WL[i], the Write Terminal to WBL[i], the Write Negated Terminal to WBLn[i], and the Read Terminal to RBL[i]. In this case, the connection between the Write Terminal and WBL[i] is switched on/off via a first transistor controlled by the Word-line Select Terminal, and the connection between the Read Terminal and RBL[i] is switched on/off via a second transistor controlled by the Word-line Select Terminal.
During a write operation on a particular bit cell (1101) the corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are accordingly set for WBL[0, 1, 2 . . . ] and WBLn[0, 1, 2 . . . ], and RBL[0, 1, 2 . . . ] are floated. The intended functional current path is shown as “(1),” with resistance Rwr. There are no unintended paths, and therefore, there are no paths which break write functionality.
Once again, the consideration related to the transistor gate overdrive requirement due to bi-polar writing arises. As current flow from the Write Terminal to the Write Negated Terminal for writing logic 1 with WL[i] setting to Vdd, WBL[i] to Vdd, and WBLn[i] to Vss, the transistors connecting the Write Terminal to WBL[i] display elevated Vgs, and Vgd=0, and therefore the drive strength of that transistor is significantly reduced. Accordingly, a typical solution to this reduced drive strength is to overdrive gate line WL[i] for that transistor, which results in a complicated design; or in increased transistor size, which reduces memory density.
In the case of a read operation (on bit cell 1102), corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are set on WBLn[0, 1, 2 . . . ], and on RBL[0, 1, 2 . . . ] to have current flow from/to WBLn[i] to/from RBL[i]. WBLn[0, 1, 2 . . . ] are set to have the same voltages as corresponding WBL[0, 1, 2 . . . ]. For read operations in this implementation, the intended functional path is shown as “(4),” with resistance Rrd. There are no unintended paths, and therefore, no related break in read functionality. Further, there does not arise a transistor gate overdrive requirement as read operations are uni-polar.
Conventional Implementation 6—2T1J SHE-MRAM
In FIG. 12, a sixth conventional implementation related to a memory array comprising SHE-MRAM memory cells comprising 2T1J structures, is depicted. Once again, each bit cell has 4 terminals: a Word-line Select Terminal, a Write Terminal, a Write Negated Terminal, and a Read Terminal. The conventional implementation for each bit cell [i] involves connecting the Word-line Select Terminal to WL[i], the Write Terminal to WBL[i], the Write Negated Terminal to WBLn[i], and the Read Terminal to RBL[i]. In this case, the connection between the Read Terminal and RBL[i] is switched on/off via a first transistor controlled by the Word-line Select Terminal, and the connection between the Write Negated Terminal and WBLn[i] is switched on/off via a second transistor controlled by the Word-line Select Terminal.
During a write operation on a particular bit cell (1201) the corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are accordingly set for WBL[0, 1, 2 . . . ] and WBLn[0, 1, 2 . . . ], and RBL[0, 1, 2 . . . ] are floated. The intended functional current path is shown as “(1),” with resistance Rwr. There are no unintended paths, and therefore, there are no paths which break write functionality.
Once again, the consideration related to the transistor gate overdrive requirement due to bi-polar writing arises. As current flow to the Write Terminal from the Write Negated Terminal for writing logic 0 with WL[i] setting to Vdd, WBL[i] to Vss, and WBLn[i] to Vdd, the transistors connecting the Write Negated Terminal to WBLn[i] display elevated Vgs, and Vgd=0, and therefore the drive strength of that transistor is significantly reduced. Accordingly, a typical solution to this reduced drive strength is to overdrive gate line WL[i] for that transistor, which results in a complicated design; or in increased transistor size, which reduces memory density.
In the case of a read operation (on bit cell 1202), corresponding selected word line is asserted, and all remaining unselected word lines are de-asserted. Appropriate voltages are set on WBL[0, 1, 2 . . . ], and on RBL[0, 1, 2 . . . ] to have current flow from/to WBL[i] to/from RBL[i]. WBLn[0, 1, 2 . . . ] are set to have the same voltages as corresponding WBL[0, 1, 2 . . . ]. For read operations in this implementation, the intended functional path is shown as “(4),” with resistance Rrd. There are no unintended paths, and therefore, no related break in read functionality. Further, there does not arise a transistor gate overdrive requirement as read operations are uni-polar.
Accordingly, it is seen that the implementation of SHE-MRAM using conventional SHE/GSHE switched MTJs (for example, as taught in International Application No. WO 2014/025838 to Buhrman et al., entitled “Electrically gated three-terminal circuits and devices based on spin hall torque effects in magnetic nanostructures,”) and as discussed above with regard to conventional implementations 1-6, suffer from numerous drawbacks. For conventional implementations 1-3 which may improve density with 1T1J structures, it is seen that there are many breaks in read/write functionalities. For 2T1J conventional implementations 4-6, adding an extra access transistor, at the cost of lower density can accomplish read/write functionality in many cases, but are not efficient due to requirements of the overdrive voltages, and other drawbacks discussed in detail above.
However, it is desirable to achieve high density memory structures which can fully exploit the advantages of SHE/GSHE, while avoiding drawbacks related to transistor gate overdrive voltages, increased transistor sizing, and need for 2T1J structures. In other words, it is desirable to achieve memory structures which include 3-terminal devices based on GSHE principles, and which can accomplish high density and superior performance, in comparison to the above conventional implementations and conventional 2-terminal STT-MTJ devices.